openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
Other
2.29k stars 691 forks source link

Debugging with Verilator, OpenOCD and GDB #569

Closed abdullahyildiz closed 3 years ago

abdullahyildiz commented 3 years ago

I'm trying to connect to Verilator simulation from GDB. However, simulation finishes before OpenOCD connects to simulation executable and opens a new GDB port:

In the first terminal window I run:

$ ./work-ver/Variane_testharness --rbb-port=38000 ~/Desktop/riscv-tests/benchmarks/dhrystone.riscv

In the second terminal window I run:

$ openocd --command 'gdb_port 0' --command 'tcl_port disabled' --command 'telnet_port disabled' -f ariane.cfg

Here is my OpenOCD config file:

interface remote_bitbang
remote_bitbang_host localhost
remote_bitbang_port 38000

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0

gdb_report_data_abort enable
gdb_report_register_access_error enable

riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120

# prefer to use sba for system bus access                                                                                                                                                                                                                                       
riscv set_prefer_sba off

# Try enabling address translation (only works for newer versions)                                                                                                                                                                                                              
if { [catch {riscv set_enable_virtual on} ] } {
    echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }

init
halt
echo "Ready for Remote Connections"

I think compiling the program with -ggdb option should be sufficient. Is there anyone who encountered this issue before?

abdullahyildiz commented 3 years ago

I noticed that I should run the simulation as follows:

./work-ver/Variane_testharness +jtag_rbb_enable=1 --rbb-port=38000 ~/Desktop/riscv-tests/benchmarks/dhrystone.riscv

This time I can successfully connect OpenOCD and GDB to simulation.

By the way, socket connection between simulation and OpenOCD is very slow. I think it is normal and expected.