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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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Vivado Simulation error #766

Closed sajjadahmed677 closed 1 year ago

sajjadahmed677 commented 2 years ago

Hello all! I am trying to simulate cva6 on vivado 2021.1 and facing an error which is unknown to me. can anyone point out the source of the error. below is the elaboration log of the simulator.

Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2021.1/bin/unwrapped/lnx64.o/xelab -wto 9ae5f3266a684ad9857215bea2c79bb5 --incr --debug all --rangecheck --mt 8 -L xil_defaultlib -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_behav xil_defaultlib.tb xil_defaultlib.glbl -log elaborate.log -sv_lib dpi 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/lzc.sv:40]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv:220]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/stream_mux.sv:41]
Completed static elaboration
WARNING: [XSIM 43-4455] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/cache_ctrl.sv" Line 457 : Unsupported feature in assertion/property/sequence 'implication operator'. It will be ignored.
WARNING: [XSIM 43-4455] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/cache_ctrl.sv" Line 459 : Unsupported feature in assertion/property/sequence 'implication operator'. It will be ignored.
WARNING: [XSIM 43-4455] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/miss_handler.sv" Line 513 : Unsupported feature in assertion/property/sequence 'Multiclocked Sequence'. It will be ignored.
WARNING: [XSIM 43-4455] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/miss_handler.sv" Line 784 : Unsupported feature in assertion/property/sequence 'Multiclocked Sequence'. It will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/miss_handler.sv" Line 787 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/miss_handler.sv" Line 790 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/tag_cmp.sv" Line 91 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 118 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 124 : The "System Verilog Assume" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 225 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 229 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 233 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 237 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 241 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 245 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 118 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 124 : The "System Verilog Assume" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 225 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 229 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 233 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 237 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 241 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv" Line 245 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/fifo_v3.sv" Line 143 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/fifo_v3.sv" Line 147 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/std_cache_subsystem.sv" Line 261 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/std_cache_subsystem.sv" Line 266 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/std_cache_subsystem.sv" Line 272 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
WARNING: [XSIM 43-4127] File "/home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/core/cache_subsystem/std_cache_subsystem.sv" Line 272 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 40, File /home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/lzc.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 40, File /home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/lzc.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 40, File /home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/lzc.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 40, File /home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/lzc.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 40, File /home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/lzc.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 40, File /home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/lzc.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 40, File /home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/lzc.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 220, File /home/sahmed/cva6/common/submodules/common_cells/src/rr_arb_tree.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 41, File /home/sahmed/projects/cva6/cl_cv6.srcs/sources_1/imports/src/stream_mux.sv
ERROR: [XSIM 43-3316] Signal SIGSEGV received.

is it due to these warnings or there is any other reason?

MikeOpenHWGroup commented 1 year ago

Hi @sajjadahmed677, thanks for your question and apologies for the very late response.

Vivado is still an incomplete SV simulator and it is not supported by CVA6. If you are an AMD/Xilinx customer I would encourage you to ask the Vivado support team to look into this.