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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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[Bug Report] Wrong type exception when access invalid memory #883

Closed chenc6 closed 10 months ago

chenc6 commented 2 years ago

Hi,

Our test cases show that when cva6 jumps to an invalid address (e.g., 0x7ff84538), it throws an Instruction Page Fault exception (at 22990ns). However, we believe it should throw the Instruction Access Fault exception based on the priority of exception from the RISC-V ISA Volume II: Privileged Architecture 20211203.

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The test mem file and RTL log are attached. wrong_excep.zip

MikeOpenHWGroup commented 1 year ago

Hi @JeanRochCoulon, this issue is more than 7 months old and has not received any updates. It looks like an important issue to me. Please assign the right person to move this along.

Jbalkind commented 1 year ago

It's possible that this was addressed by the MMU changes in #968 but I'm not 100% sure. Worth checking

JeanRochCoulon commented 1 year ago

Hi André, as this GitHub issue is related to the traps, I feel good to assign it to you.

ASintzoff commented 10 months ago

According to Table 3.7 of RISC-V ISA Volume II: Privileged Architecture 20211203, the priority of page fault or access fault during instruction address translation is determined by the first one encountered. Therefore the CVA6 behaviour is compliant with RISC-V specification.

BTW the exception cause code is not related at all to the exception priority.