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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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CV32A6 Design Document includes floating point CSRs #997

Closed MikeOpenHWGroup closed 9 months ago

MikeOpenHWGroup commented 2 years ago

Is there an existing CVA6 bug for this?

Bug Description

The register description section of the CV32A6 Design Document lists a set of RV32F floating point CSRs. As far as I am aware, the CV32A6 does not support floating point, so these registers should not exist and therefore not be part of the Design Document.

spidugu444 commented 1 year ago

In CV32A6 Design Document there are group of trigger registers which has not been implemented in CVA6 RTL. As these registers has not been implemented therefore these will not to be part of the Design Document. Please find the details of trigger registers as mentioned below.

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tselect | 0x7A0 -- | -- tdata1 | 0x7A1 tdata2 | 0x7A2 tdata3 | 0x7A3 tinfo | 0x7A4

JeanRochCoulon commented 9 months ago

The FPU and trigger CSrs have been removed from Design Document, please refer to : https://docs.openhwgroup.org/projects/cva6-user-manual/04_cv32a6_design/source/csr_list.html