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openhwgroup / cve2

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/
Apache License 2.0
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[BUG] When executing MRET the CSRs mepc and mcause are updated. #176

Open LeeHoff opened 6 months ago

LeeHoff commented 6 months ago

Bug Description

When running the interrupt_test with USE_ISS=YES, the RTL fails when compared to the reference model.

According to the RISCV priv specification “When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, mepc is never written by the implementation, though it may be explicitly written by software.” This statement is also true for mcause.

LeeHoff commented 6 months ago

The error happens at 381801.8 nSec and the output looks like this:

Info 16697: 'refRoot/cpu', 0x00000000000012d2(m_nmi_irq_handler+90): Machine 30200073 mret Info mstatus 00001880 -> 00000088 [SD:0 TW:0 MPRV:0 XS:0(Off) FS:0(Off) MPP:3->0 VS:0(Off) MPIE:1 UBE:0 MIE:0->1] Info (IDV) Instruction executed prior to mismatch '0x12d2(m_nmi_irq_handler+90): 30200073 mret' Error (IDV) CSR register value mismatch (HartId:0, PC:0x000012d2 m_nmi_irq_handler+90): Error (IDV) Mismatch 0> CSR 341 (mepc) Error (IDV) . dut:0x000013c2 Error (IDV) . ref:0x000014a8 (not updated) Error (IDV) Mismatch 1> CSR 342 (mcause) Error (IDV) . dut:0x8000001e Interrupt:1 Code:30 Error (IDV) . ref:0x80000020 Interrupt:1 Code:32 (not updated) UVM_ERROR @ 381801.800 ns : idvPkg.sv(59) reporter [] uvmt_cv32e20_tb.imperas_dv.trace2api.state_compare @ 381802.000 ns: MISMATCH