Random instruction generator

[DBees]

This task is complete when:

• the riscv-dv random instruction stream generator is integrated into the UVM verification environment.
• the corev-dv extension mechanism is in place for CV32E20.
• the Makefiles have been updated to generate, compile and run corev-dv test-programs. For example:

  $ make corev-dv CV_CORE=cv32e20 SIMULATOR=vsim
  $ make comp CV_CORE=cv32e20 SIMULATOR=vsim
  $ make test COREV=YES TEST=hello-world SIMULATOR=vsim
  $ make gen_corev-dv test TEST=corev_rand_interrupt SIMULATOR=vsim

[MikeOpenHWGroup]

We are almost there. @MarioOpenHWGroup reports that the following invocation of corev-dv is working:

git clone git@github.com:openhwgroup/core-v-verif
cd core-v-verif
git clone git@github.com:Marioopenhwgroup/cv32e20-dv -b feature/interrupts  cv32e20
git clone git@github.com:MarioOpenhwgroup/cve2 -b feature/rvfi_improvements core-v-cores/cv32e20
make -C cv32e20/sim/uvmt/ comp_corev-dv test TEST=corev_rand_interrupt SIMULATOR=vsim USE_ISS=yes

There are still a few items to resolve before this Task can be closed:

1. The feature/interrupts branch of cv32e20-dv must be merged to the main branch.
2. The feature/rvfi_improvements branch of cve2 must be merged to the main branch.
3. We need to resolve the action of the USE_ISS variable. Up to now, all other UVM environments for the embedded cores (E40* and E20) have used USE_ISS to control usage of the ImperasDV reference model. It appears that we are now using it to control usage of Spike.