The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Establishing the numbers:
VendorID is from JEDEC - we have this
ArchID is assigned from RISC-V and indicates the processor - not done yet
ImpID is 0 as it is the first implementation of this architecture
Establishing the numbers: VendorID is from JEDEC - we have this ArchID is assigned from RISC-V and indicates the processor - not done yet ImpID is 0 as it is the first implementation of this architecture
Documentation not updated