The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
The objective of the task is to have a UVM environment capable of processing RISC-V instructions retired by the core. This is required to send the instructions to the subscribers in the UVM environment as coverage or Reference Model for step-by-step comparisons.
The objective of the task is to have a UVM environment capable of processing RISC-V instructions retired by the core. This is required to send the instructions to the subscribers in the UVM environment as coverage or Reference Model for step-by-step comparisons.