The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
As of 2023-12-30, the CORE-V-VERIF UVM environment supported the ImperasDV reference model. At this time none of the OpenHW Contributors to this project have access to an ImperasDV license, so it is possible that future updates to the environment will introduce a bug that prevents ImperasDV from running.
This task can be completed if-and-when a Contributor with an ImperasDV license tests (and if required, restores) ImperasDV-as-a-reference-model.
As of 2023-12-30, the CORE-V-VERIF UVM environment supported the ImperasDV reference model. At this time none of the OpenHW Contributors to this project have access to an ImperasDV license, so it is possible that future updates to the environment will introduce a bug that prevents ImperasDV from running.
This task can be completed if-and-when a Contributor with an ImperasDV license tests (and if required, restores) ImperasDV-as-a-reference-model.