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openhwgroup / cve2

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/
Apache License 2.0
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Inject asynchronous events in a reference model #265

Open DBees opened 2 months ago

MarioOpenHWGroup commented 2 months ago

Interrupts injection has been implemented on the UVM testbench. There are some problems with the tracer and the MIP register as it can be set and unset between two rvfi_valid.

MarioOpenHWGroup commented 2 months ago

Interrupts already working, currently I have the following result with ci_check

PRs already opened in the three repositories: cve2, core-v-verif, cv32e20-dv Output: 

CI Check results:
                     vsim-debug_test.log : ABORTED
    vsim-corev_rand_jump_stress_test.log :  PASSED
               vsim-csr_instructions.log :  PASSED
                 vsim-interrupt_test.log :  PASSED
                        vsim-illegal.log :  PASSED
          vsim-corev_rand_instr_test.log :  PASSED
                    vsim-hello-world.log :  PASSED
vsim-corev_rand_arithmetic_base_test.log :  PASSED
  vsim-riscv_arithmetic_basic_test_0.log :  PASSED
           vsim-corev_rand_interrupt.log :  PASSED
           vsim-corev_rand_interrupt.log :  PASSED
MarioOpenHWGroup commented 1 month ago

Infrastructure for Debug Mode is in place, injection into Spike works but there are mismatches when the core enters to the Debug Mode.

MarioOpenHWGroup commented 1 month ago

https://github.com/openhwgroup/cve2/pull/266 https://github.com/openhwgroup/cv32e20-dv/pull/2/files https://github.com/openhwgroup/core-v-verif/pull/2412

MarioOpenHWGroup commented 1 month ago

The RTL tracer is not currently working well with debug requests so it will need some extra RTL work. Currently the test is executing but not finishing correctly

MarioOpenHWGroup commented 1 month ago 
CI Check results:
    vsim-corev_rand_jump_stress_test.log :  PASSED
               vsim-csr_instructions.log :  PASSED
                 vsim-interrupt_test.log :  PASSED
                        vsim-illegal.log :  PASSED
                     vsim-debug_test.log :  PASSED
          vsim-corev_rand_instr_test.log :  PASSED
                    vsim-hello-world.log :  PASSED
vsim-corev_rand_arithmetic_base_test.log :  PASSED
  vsim-riscv_arithmetic_basic_test_0.log :  PASSED
           vsim-corev_rand_interrupt.log :  PASSED
           vsim-corev_rand_interrupt.log :  PASSED

CI Check PASSED with no failures.
OK to issue a pull-request.
MarioOpenHWGroup commented 1 month ago

All CI tests are passing, including debug