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openhwgroup / cve2

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/
Apache License 2.0
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[BUG] <misalgined access> #267

Open Jiahua-Gong opened 4 months ago

Jiahua-Gong commented 4 months ago

Bug Description

obi2ahbm_adapter.sv.. if byte access 24bits , bridge don't split 2 trans

MikeOpenHWGroup commented 4 months ago

Thanks for creating this issue @shanshuixiangyi.

Hi @davideschiavone, I have added both bug and question labels to this issue as I am not sure if this feature is supported by the CVE2. If it is not, then the OBI2AHB bridge does not need to support this. If that is the case, we should clearly document the behavior of the bridge.

davideschiavone commented 4 months ago

hi @MikeOpenHWGroup and @shanshuixiangyi - the CVE2 supports misaligned on the OBI interface, so it is very well possible that the bridge has this bug -

MikeOpenHWGroup commented 4 months ago

Thanks @davideschiavone, I have removed the question label and this is now officially a bug! :wink:

Hi @shanshuixiangyi, do you have an example test-program to exercise this?

Jiahua-Gong commented 4 months ago

图片 risc-v load store uint can transmit red select in the pitcture. but bridge can't support this byte condition. I have modified the rtl to support this condition. I am learning how to submit code and then make a fix commit using Git.

MikeOpenHWGroup commented 4 months ago

I am learning how to submit code and then make a fix commit using Git.

Thank you very much @Jiahua-Gong! I notice that the CONTRIBUTING file for this repo is not complete (I will fix that). In the meantime, please review CONTRIBUTING.md in CORE-V-VERIF, especially the Contributor Agreement section.