openhwgroup / cve2

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/
Apache License 2.0
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Update the interrupt vector table in the documentation #273

Open DanieleParravicini-Synthara opened 5 months ago

MikeOpenHWGroup commented 5 months ago

Hi @DanieleParravicini-Synthara. I recommend that we have a (virtual) in-person discussion with @davideschiavone and @MarioOpenHWGroup before we proceed much future with this PR. In the meantime, you will need to be covered by the Eclipse Contributor Agreement before any PRs from you can be accepted. As Synthara is an OpenHW Group member, it is best for you to use a GitHub repo associated with your employer, rather than a person account.

DanieleParravicini commented 5 months ago

Will change the signature

DanieleParravicini-Synthara commented 5 months ago

Hello @MikeOpenHWGroup, I changed the signature of all the commits. Sure, MaurizioCapra( the guy in charge of RISC-V development in synthara ) and I would be available for a call

DanieleParravicini-Synthara commented 5 months ago

In the meanwhile I will ask to complete the ECA

MikeOpenHWGroup commented 5 months ago

In the meanwhile I will ask to complete the ECA

Hi @DanieleParravicini. I see that you are now properly covered by the ECA using your Synthara credentials. However, there are still at least two commits in this PR from non-Synthata credentials and these will block the merge. You have two options:

  1. Rebase the commits on this PR.
  2. Close this PR and submit a fresh one from your Synthara credentials.
DanieleParravicini-Synthara commented 5 months ago

Hey @MikeOpenHWGroup, sorry for the mistake.

They should be rebased now

DanieleParravicini-Synthara commented 5 months ago

The PR itself is not much but I hope it can help

DanieleParravicini-Synthara commented 5 months ago

So you think that I got this right?