openhwgroup / cve2

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/
Apache License 2.0
29 stars 25 forks source link

Clean up and Complete Input/Output ports of CVE2 #6

Open davideschiavone opened 2 years ago

davideschiavone commented 2 years ago

Depending on the output of the issues #5, #4, #3, and #2

the following signals should probably be removed:

  // Register file interface
  output logic                         dummy_instr_id_o,
  output logic [4:0]                   rf_raddr_a_o,
  output logic [4:0]                   rf_raddr_b_o,
  output logic [4:0]                   rf_waddr_wb_o,
  output logic                         rf_we_wb_o,
  output logic [RegFileDataWidth-1:0]  rf_wdata_wb_ecc_o,
  input  logic [RegFileDataWidth-1:0]  rf_rdata_a_ecc_i,
  input  logic [RegFileDataWidth-1:0]  rf_rdata_b_ecc_i,

  // RAMs interface
  output logic [IC_NUM_WAYS-1:0]       ic_tag_req_o,
  output logic                         ic_tag_write_o,
  output logic [IC_INDEX_W-1:0]        ic_tag_addr_o,
  output logic [TagSizeECC-1:0]        ic_tag_wdata_o,
  input  logic [TagSizeECC-1:0]        ic_tag_rdata_i [IC_NUM_WAYS],
  output logic [IC_NUM_WAYS-1:0]       ic_data_req_o,
  output logic                         ic_data_write_o,
  output logic [IC_INDEX_W-1:0]        ic_data_addr_o,
  output logic [LineSizeECC-1:0]       ic_data_wdata_o,
  input  logic [LineSizeECC-1:0]       ic_data_rdata_i [IC_NUM_WAYS],
  input  logic                         ic_scr_key_valid_i,

  output crash_dump_t                  crash_dump_o,
  // SEC_CM: EXCEPTION.CTRL_FLOW.LOCAL_ESC
  // SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC
  output logic                         double_fault_seen_o,

  output logic                         alert_minor_o,
  output logic                         alert_major_o,
  output logic                         icache_inval_o,
  output logic                         core_busy_o

  // Interrupt inputs
  input  logic                         irq_software_i,
  input  logic                         irq_timer_i,
  input  logic                         irq_external_i,
  input  logic [14:0]                  irq_fast_i,
  input  logic                         irq_nm_i,       // non-maskeable interrupt
  output logic                         irq_pending_o,

these added:

 input logic [31:0] mtvec_addr_i,
 input logic [31:0] dm_halt_addr_i,
 input logic [31:0] dm_exception_addr_i,

 output logic debug_havereset_o,
 output logic debug_running_o,
 output logic debug_halted_o,

 output logic core_sleep_o,

 // Interrupt inputs
 input  logic [31:0] irq_i,  // CLINT interrupts + CLINT extension interrupts
 output logic        irq_ack_o,
 output logic [ 4:0] irq_id_o,
joecircello commented 1 year ago

Lee Hoff and I discussed this issue on Dec 5, 2022 and agree with Davide's proposal with one change - we believe there is a need for an output signal indicating the core has detected a "double fault condition", that is, double_fault_seen_o.