When csrtests.py has minstret after mcycleh in the mregs list, the last cycle of walking 1s through minstret hangs lockstep or lockstepverbose simulation. There is no hang for nonlockstep sim.
Commented out minstret until this is resolved.
~/cvw/addins/cvw-arch-verif$ bin/csrtests.py; make build; wsim rv64gc tests/priv/ZicsrM.elf --lockstepverbose
# Info 19889: 'refRoot/cpu', 0x00000000800057d4(postmrettest+3c8): Machine 00129293 slli x5,x5,0x1
# Info MEMX 0x800057d4 0x800057d4 2 9293
# Info MEMX 0x800057d6 0x800057d6 2 0012
# Info x5 4000000000000000 -> 8000000000000000
# Info 19890: 'refRoot/cpu', 0x00000000800057d8(postmrettest+3cc): Machine fe029ae3 bnez x5,800057cc
# Info MEMX 0x800057d8 0x800057d8 2 9ae3
# Info MEMX 0x800057da 0x800057da 2 fe02
# Info 19891: 'refRoot/cpu', 0x00000000800057cc(postmrettest+3c0): Machine b0232ff3 csrrs x31,minstret,x6
# Info MEMX 0x800057cc 0x800057cc 2 2ff3
# Info MEMX 0x800057ce 0x800057ce 2 b023
# Info x31 ffffffffffffffff -> c000000000000001
# Info 19892: 'refRoot/cpu', 0x00000000800057d0(postmrettest+3c4): Machine b022bff3 csrrc x31,minstret,x5
# Info MEMX 0x800057d0 0x800057d0 2 bff3
# Info MEMX 0x800057d2 0x800057d2 2 b022
# Info x31 c000000000000001 -> ffffffffffffffff
# Break key hit
When csrtests.py has minstret after mcycleh in the mregs list, the last cycle of walking 1s through minstret hangs lockstep or lockstepverbose simulation. There is no hang for nonlockstep sim.
Commented out minstret until this is resolved.