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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Code coverage improvements
#1075
Closed
jordancarlin
closed
2 weeks ago
jordancarlin
commented
2 weeks ago
time CSR
illegal aes64ksli1
remove unused fround coverage test file
refactor machine code instructions to use assembly mnemonics that are supported in newer compilers