CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
As discussed here https://gitlab.com/qemu-project/qemu/-/issues/2660, QEMU will automatically initialize the submodules that it needs. This is only a small fraction of the submodules present in the project. This avoids downloading unnecessary components that waste time and space. Also has the side-effect of fixing #1070.
As discussed here https://gitlab.com/qemu-project/qemu/-/issues/2660, QEMU will automatically initialize the submodules that it needs. This is only a small fraction of the submodules present in the project. This avoids downloading unnecessary components that waste time and space. Also has the side-effect of fixing #1070.