CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Discovered while working on fetch buffer. Assertions in riscvassertions.sv were not being checked by Verilator. This enables them to avoid invalid configs from being simulated.
Discovered while working on fetch buffer. Assertions in riscvassertions.sv were not being checked by Verilator. This enables them to avoid invalid configs from being simulated.