search

openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Other
272 stars 198 forks source link

Update fetch buffer branch from main #1087

Closed jordancarlin closed 1 week ago

jordancarlin commented 1 week ago

Primarily want to get Verilator assertions added