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openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Fixes lint warnings in loggers.sv updates spi device tree for vcu108 #1088

Closed rosethompson closed 2 weeks ago

rosethompson commented 2 weeks ago

Worked with Kaitlin to fix the lint warnings preventing her from making progress from including benchmarks in the nightly regression tests. Updated spi clock frequency so it works correctly with vcu108.

rosethompson commented 2 weeks ago

Yes

rosethompson commented 2 weeks ago

Well this is interesting. We tested this with verilator but not questa and questa is not happy with loggers.sv. I'm going to convert to a draft and fix.

jordancarlin commented 2 weeks ago

Strange. What is Verilator complaining about in the original version?

Also, we've been able to get away using bitwise operators everywhere else so it would also be nice to stick with that if possible instead of switching to logical operators. Was Verilator complaining about them otherwise?

rosethompson commented 2 weeks ago

Questa gave an error about TEST not being constant inside a generate which makes sense because it's a plus arg. Verilator seems to be ok with this. I've refactored the code to avoid the generate.

I removed the logic operators. Kaitlin and I were having issues with the bitwise operators throwing bitwidth warnings with Verilator, but after the other issues have been fixed these seem to have gone away as well.

rosethompson commented 2 weeks ago

@jordancarlin Are you happy with the changes? If so I'd like to get this merged so @slmnemo can work on integrating performance monitoring in the nightly regression.