added Zicsr (32 and 64) to run in Imperas

openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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added Zicsr (32 and 64) to run in Imperas #1094

Closed ahlyssa closed 1 week ago

davidharrishmc commented 1 week ago

Please make a concurrent cvw-arch-verif PR to create the tests so they can be found when you run them.