CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
When debugging #1066 , cvw-arch-verif tests showed that FRoundNX did not handle NaNs correctly. Per the spec, the NX flag should only be raised if the input is not NaN, however the Incorrect NaN-boxing tests demonstrated that this was not the case.
In #1093 this was fixed, adding an additional condition to the logic for the FRoundNX signal in fround.sv
When debugging #1066 , cvw-arch-verif tests showed that FRoundNX did not handle NaNs correctly. Per the spec, the NX flag should only be raised if the input is not NaN, however the Incorrect NaN-boxing tests demonstrated that this was not the case.
In #1093 this was fixed, adding an additional condition to the logic for the
FRoundNXsignal infround.sv