openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Update riscv-arch-test with PMP and sv32 VM #1102

Closed jordancarlin closed 1 week ago

jordancarlin commented 1 week ago

Opening this PR despite it being in a somewhat iffy state because UET needs this for VM functional coverage. Doesn't break anything so should be fine to merge.