Made minor changes to the controller to clean up the logic. Still need to simplify the first always block.

openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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Made minor changes to the controller to clean up the logic. Still need to simplify the first always block. #1103

Open JacobPease opened 1 week ago

jordancarlin commented 1 week ago

@JacobPease looks like a merge conflict now

JacobPease commented 1 week ago

Weird. I just changed this file after pulling. I'll look into it.

jordancarlin commented 1 week ago

Pretty sure it was a lint_off issue that I fixed. Should be an easy resolution.

jordancarlin commented 1 week ago

You seem to have accidentally reverted other recent PRs when fixing the merge conflict...