openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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SPI code cleanup #1108

Closed davidharrishmc closed 3 hours ago

davidharrishmc commented 4 hours ago

In spi_apb.sv:

davidharrishmc commented 4 hours ago

@JacobPease can you take a look at this one?

JacobPease commented 4 hours ago

@JacobPease can you take a look at this one?

I think that's something left from trying to fix the previous SPI code. At one point the conditions were different. I can fix that and add it to my current PR.

JacobPease commented 3 hours ago

@davidharrishmc Fixed. Still passes regression too.

davidharrishmc commented 3 hours ago

Speedy!