Add ExceptionM to fcov - Githubissues

openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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Add ExceptionM to fcov #1118

Closed coreyqh closed 2 days ago

coreyqh commented 3 days ago

Adds ExceptionM covergroup to fcov along with some definitions that are used in that covergroup
MUST BE MERGED WITH openhwgroup/cvw/#321 EITHER ONE ON THEIR OWN HANGS --FCOV