davidharrishmc
commented
1 year ago Ethan,
It’s nice to meet you. It’s great to see architecture courses getting focused around a processor with real RTL.
Our course website is at http://pages.hmc.edu/harris/class/e154/
Our labs involve:
- Set up environment
- Write assembly language program to optimize a FIR filter.
- Write a test case generator and run logic verification tests
- Check out a fork of the repository with four bugs and find them through Verilog simulation
- Synthesize and try to optimize the rv32e core
- Design the logic for mulhsu
Last year our final project involved designing a half-precision FMA, and this year we are working on test coverage.
Your labs sound great too!
We’re working on a textbook associated with the processor, and have decent drafts of 13 of the 20 chapters so far. If you’d be interested in reviewing, we are happy to share.
David
On Apr 2, 2023, at 6:09 PM, Ethan Sifferman @.***> wrote:
Hi, Dr. Harris. I was recommended to reach out to you by Rick O'Connor, who I met at the conference "Latch-Up" this weekend.
As an education researcher at UCSB, I helped rewrite our advanced architecture class to be based around CVA6. The class was taught last quarter, and students seemed to really enjoy it and learn a lot! I presented the class at "Latch-Up" this weekend, and Rick O'Connor recommended that I reach out to you in case we could share any ideas. I would be happy to help contribute to Wally if you see anything from our course you think would be a helpful addition to your upcoming textbook.
Here is a quick summary of each of our labs, (all are open-source):
Branch Prediction https://github.com/sifferman/labs-with-cva6/blob/main/labs/branch-prediction.md: Students modify the existing CVA6 saturation counter predictor into a global predictor. SystemVerilog Practice https://github.com/sifferman/labs-with-cva6/blob/main/labs/sv.md: Students implement a FIFO and are forced to write SystemVerilog that infers a BRAM. Caching https://github.com/sifferman/labs-with-cva6/blob/main/labs/caching.md: Students implement a victim-cache, and add it to CVA6 Out-of-Order https://github.com/sifferman/labs-with-cva6/blob/main/labs/ooo.md: Students write an assembly program to demonstrate out-of-order, WAW, WAR, RAW. Virtual Memory https://github.com/sifferman/labs-with-cva6/blob/main/labs/vm.md: Students are given a simple bootloader and OS https://github.com/sifferman/labs-with-cva6/blob/main/programs/vm/os.S that enables virtual memory, then students add an additional page table entry Thanks for creating so many great resources for learning, and I am happy to talk further!
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Hi, Dr. Harris. I was recommended to reach out to you by Rick O'Connor, who I met at the conference "Latch-Up" this weekend.
As an education researcher at UCSB, I helped rewrite our advanced architecture class to be based around CVA6. The class was taught last quarter, and students seemed to really enjoy it and learn a lot! I presented the class at "Latch-Up" this weekend, and Rick O'Connor recommended that I reach out to you in case we could share any ideas. I would be happy to help contribute to Wally if you see anything from our course you think would be a helpful addition to your upcoming textbook.
Here is a quick summary of each of our labs, (all are open-source):
Thanks for creating so many great resources for learning, and I am happy to talk further!