More tests in nightly regression

openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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More tests in nightly regression #779

Open davidharrishmc opened 3 months ago

davidharrishmc commented 3 months ago

Performance validation: CoreMark, Embench, cache, branch, ways to detect issues Tests with multiple simulators Lockstep tests Code coverage Functional coverage

Some of this depends on having a single test bench that supports lockstep, and replacing run-elf / run-elf-cov, iter-elf.

Update testplan.md when done

davidharrishmc commented 3 months ago

VCS added to nightly regression. Verilator too.

davidharrishmc commented 1 month ago

Added lockstep tests of coverage and wally-riscv-arch-test privilege with iterelf PR #866 Added lockstep test of buildroot boot