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openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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IgnoreRequest logic in IFU and LSU #839

Open ross144 opened 2 months ago

ross144 commented 2 months ago

Think through the purpose of IgnoreRequest in the IFU and LSU. It is unused in the IFU and only use by atomic in the LSU. IgnorerRequestTLB is generated by the HPTW to assert HPTWFaults and TLB misses.

ross144 commented 2 months ago

This is the unused code from the IFU. Lines 214 to 215.

  logic  IgnoreRequest; // *** unused; RT: is this a bug or delete?
  assign IgnoreRequest = ITLBMissF | FlushD;
ross144 commented 2 months ago

In lrsc.sv Line 48.

// possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.