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openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Review SPI clock modes #898

Open ross144 opened 1 month ago

ross144 commented 1 month ago

Jacob implemented SPI on the FPGA and found issues with the SPI phase and polarity controls. Need to verify these are all correct.

davidharrishmc commented 1 month ago

@naichewa are you still reading this? If so, could you check with @JacobPease about the issue and see if you concur and have a fix?

naichewa commented 1 month ago

Sure, no problem

ross144 commented 1 month ago

There is also another issue here. The SPI module isn't working over 5Mhz on the Arty A7. I believe the underlying issue is how the SPIIn is sampled by PCLK rather than SPICLK. The FPGA is inserting a large clock latency between PCLK and SPICLK so because SPIIn is timed relative to SPICLK synthesis doesn't align SPIIn to PCLK. We could probably solve this by just changing the timing constraint, but I don't think this is the right thing to do.

SPI samples SPIIn on either the rising or falling edge of SPICLK depending on the operating mode. Since we aren't doing this I don't think the SPI module will work in any other clock mode than transmit on the falling edge and sample on the rising. I believe the correct action is to sample SPIIn using SPICLK.

JacobPease commented 3 weeks ago

I think we can now close this as of #922.