CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Fixes the 32-bit vs 64-bit library issues between Questa and ImperasDV
Modifies the FPGA to support SPI debugging. Note the FPGA is in flux and may require some specific tweak to build correctly.
Fixes the 32-bit vs 64-bit library issues between Questa and ImperasDV Modifies the FPGA to support SPI debugging. Note the FPGA is in flux and may require some specific tweak to build correctly.