Testfloat updates - Githubissues

openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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Testfloat updates #968

Closed jordancarlin closed 1 month ago

jordancarlin commented 1 month ago

Only generate RISC-V testfloat testvectors to avoid additional complexity and space requirements of maintaining both ieee and riscv vectors
Update floating-point example Makefiles to use the new version of SoftFloat