CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Update to newest version of riscv-arch-test submodule
Update d_fma tests to use new format
Add the new misalign1-cjalr and misalign1-cjr tests to the list of compressed tests to run
Test List (tests.vh and testbench.sv)
Remove outdated tests from tests.vh (imperas tests and wally64covi) fixes #969
Update formatting and whitespace of tests.vh
Remove deprecated testgen scripts and wally32i and wally64i tests
Remove unused wally64d test
Test Generation (Makefiles)
Update sim/Makefile and tests/riscof/Makefile for increased parallelism and robustness. They can now be run with make --jobs and compile all tests in less than 4 minutes on chips (compared to 15 before)
riscv-arch-test
riscv-arch-testsubmoduled_fmatests to use new formatmisalign1-cjalrandmisalign1-cjrtests to the list of compressed tests to runTest List (
tests.vhandtestbench.sv)tests.vh(imperas tests and wally64covi) fixes #969tests.vhwally32iandwally64itestswally64dtestTest Generation (
Makefiles)sim/Makefileandtests/riscof/Makefilefor increased parallelism and robustness. They can now be run withmake --jobsand compile all tests in less than 4 minutes on chips (compared to 15 before)