CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Checks if the TLB misses and if so suppresses load and store misaligned faults. Added non-self checking test to verify behavior. ImperasDV does not match. I believe there may be a different bug either with ImperasDV or our implementation. The test uses PBMT to make a misaligned uncached request with a TLB miss. The TLB correctly suppresses the fault until the TLB is filled. However, ImperasDV says the load should not cause the fault.
Checks if the TLB misses and if so suppresses load and store misaligned faults. Added non-self checking test to verify behavior. ImperasDV does not match. I believe there may be a different bug either with ImperasDV or our implementation. The test uses PBMT to make a misaligned uncached request with a TLB miss. The TLB correctly suppresses the fault until the TLB is filled. However, ImperasDV says the load should not cause the fault.