ImperasDV PBMT misaligned Mismatch

openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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ImperasDV PBMT misaligned Mismatch #976

Open rosethompson opened 1 day ago

rosethompson commented 1 day ago

PBMT configured misaligned addresses do not agree between ImperasDV and Wally.

wsim rv64gc tests/coverage/tlbMisaligned.S --lockstep

 Info (IDV) Instruction executed prior to mismatch '0x8001503c(main+3c): 929e     add     x5,x5,x7'
# Error (IDV) PC mismatch (HartId:0, PC:0x000000008001503e main+3e):
# Error (IDV) Mismatch 0>
# Error (IDV)   . dut:0x0000000080000050 
# Error (IDV)   . ref:0x000000008001503e main+3e

rosethompson commented 23 hours ago

I think this might come down to how the spec is interpreted.

Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.

Since PMBT is used to disable cacheablity I believe it should not support misaligned access even though the memory physically does support misaligned.