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openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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ImperasDV PBMT misaligned Mismatch #976

Open rosethompson opened 1 month ago

rosethompson commented 1 month ago

PBMT configured misaligned addresses do not agree between ImperasDV and Wally.

wsim rv64gc tests/coverage/tlbMisaligned.elf --lockstep

 Info (IDV) Instruction executed prior to mismatch '0x8001503c(main+3c): 929e     add     x5,x5,x7'
# Error (IDV) PC mismatch (HartId:0, PC:0x000000008001503e main+3e):
# Error (IDV) Mismatch 0>
# Error (IDV)   . dut:0x0000000080000050 
# Error (IDV)   . ref:0x000000008001503e main+3e
rosethompson commented 1 month ago

@eroom1966 I think this might come down to how the spec is interpreted.

Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.

Since PMBT is used to disable cacheablity I believe it should not support misaligned access even though the memory physically does support misaligned.

rosethompson commented 1 month ago

My attempt to generate the debug database resulted in a segfault.

I added this to the vlog command. +define+IDV_INCLUDE_TRACE2BIN

and set this variable before calling questa. IMPERAS_RVVI_DEBUG=1


# Platform = "linux_x86_64"
# Signature = ce21318267b9d07e1c15c754173193d2
# --> START OF USERCODE
# 0    0x00007ffff2825114: 'rvviDebugCaptureClock + 0x0000000000000054' in '/opt/riscv/ImperasDV-OpenHW/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model.so'
# <-- END OF USERCODE
# 1    0x00007feff05a3718: '/opt/riscv/ImperasDV-OpenHW/ImpProprietary/source/host/idv/trace2bin.sv:24'
# 2    0x00007feff416c2c5: '/opt/riscv/ImperasDV-OpenHW/ImpProprietary/source/host/idv/trace2bin.sv:193'
# 3    0x00000000023e5c82: '<unknown (@0x23e5c82)>'
# 4    0x00000000004df304: '<unknown (@0x4df304)>'
# 5    0x000000000074da13: '<unknown (@0x74da13)>'
# 6    0x0000000000ca62ed: '<unknown (@0xca62ed)>'
# 7    0x0000000000cab610: '<unknown (@0xcab610)>'
# 8    0x0000000000cacf8e: '<unknown (@0xcacf8e)>'
# 9    0x0000000000f9c58d: '<unknown (@0xf9c58d)>'
# 10   0x000000000287b08d: '<unknown (@0x287b08d)>'
# 11   0x000000000287f4e6: '<unknown (@0x287f4e6)>'
# 12   0x0000000002880bd1: '<unknown (@0x2880bd1)>'
# 13   0x0000000002880f36: '<unknown (@0x2880f36)>'
# 14   0x000000000122f669: '<unknown (@0x122f669)>'
# 15   0x0000000002920e3f: '<unknown (@0x2920e3f)>'
# 16   0x00000000029749b7: '<unknown (@0x29749b7)>'
# 17   0x00000000029378a7: '<unknown (@0x29378a7)>'
# 18   0x0000000002937b89: '<unknown (@0x2937b89)>'
# 19   0x0000000002708d7d: '<unknown (@0x2708d7d)>'
# 20   0x0000000000c6e53c: '<unknown (@0xc6e53c)>'
# End of Stack Trace

# ** Fatal: (SIGSEGV) Bad handle or reference.
#    Time: 0 ns  Iteration: 1  Process: /testbench/rvvi/#ALWAYS#114 File: /opt/riscv/ImperasDV-OpenHW/ImpProprietary/source/host/idv/trace2bin.sv
# Fatal error at /opt/riscv/ImperasDV-OpenHW/ImpProprietary/source/host/idv/trace2bin.sv line 24
# 
# HDL call sequence:
# Stopped at /opt/riscv/ImperasDV-OpenHW/ImpProprietary/source/host/idv/trace2bin.sv 24  
# called from  /opt/riscv/ImperasDV-OpenHW/ImpProprietary/source/host/idv/trace2bin.sv 193  
# 
# End time: 08:55:28 on Oct 14,2024, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
rosethompson commented 1 month ago

tlbMisaligned.tar.gz