Report on Verilator modeling to HW Task Group meeting 20 Oct 2021.

openhwgroup / programs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

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Closed jeremybennett closed 2 years ago

jeremybennett commented 2 years ago

Files changed:

* hw/projects/verilator-model/2021/20211020-hwtg-report.md: Created.

Signed-off-by: Jeremy Bennett jeremy.bennett@embecosm.com