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Documentation for the OpenHW Group's set of CORE-V RISC-V cores
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More undefined conditions for HW loops #567

Closed tzwaenn closed 1 year ago

tzwaenn commented 1 year ago

There are various conditions listed in the user manual on undefined behavior for hardware loops for CV32E40P. Looking at this during some experiments for hardware loop support for the Siemens RISC-V verification app with formal verification, some more potentially undefined cases were identified that no sane compiler will generate:

MikeOpenHWGroup commented 1 year ago

Hi @tzwaenn, thanks for creating this issue. Unfortunately this is not the correct place for it, so I have opened CV32E40P issue #748 and will close this one.