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Documentation for the OpenHW Group's set of CORE-V RISC-V cores
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Draft PL and PA documents for Verilator modeling. #596

Closed jeremybennett closed 1 year ago

jeremybennett commented 1 year ago 
The PL document that existed was very out-of-date, so has largely
been written and simplified.

Project-Descriptions-and-Plans/

* MCU-Verilator-Model/verilator-modeling-pa.md: Created.
* MCU-Verilator-Model/verilator-modeling-pl.md: Updated.