Closed editorialbot closed 1 year ago
editorialbot
commented
2 years ago Hello humans, I'm @editorialbot, a robot that can help you with some common editorial tasks.
For a list of things I can do to help you, just type:
@editorialbot commandsFor example, to regenerate the paper pdf after making changes in the paper's md or bib files, type:
@editorialbot generate pdfSoftware report:
github.com/AlDanial/cloc v 1.88 T=0.16 s (555.8 files/s, 192120.5 lines/s)
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Language files blank comment code
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JavaScript 14 2405 2473 9223
HTML 22 2952 66 6383
Python 27 1008 1647 2916
TeX 2 70 14 376
Coq 1 40 0 257
reStructuredText 10 207 88 233
Markdown 7 81 0 203
YAML 2 6 18 31
DOS Batch 1 8 1 26
TOML 1 1 0 9
make 1 4 7 9
Verilog-SystemVerilog 1 0 0 4
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SUM: 89 6782 4314 19670
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gitinspector failed to run statistical information for the repositoryWordcount for paper.md is 1360
editorialbot
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2 years ago Reference check summary (note 'MISSING' DOIs are suggestions that need verification):
OK DOIs
- 10.1063/1.5001312 is OK
- 10.1016/j.bpj.2021.11.1391 is OK
- 10.5281/zenodo.777229 is OK
- 10.1080/08940886.2019.1608121 is OK
MISSING DOIs
- 10.1145/2851581.2890266 may be a valid DOI for title: FrontPanel®
INVALID DOIs
- https://doi.org/10.5281/zenodo.3732545 is INVALID because of 'https://doi.org/' prefix:point_right::page_facing_up: Download article proof :page_facing_up: View article proof on GitHub :page_facing_up: :point_left:
danielskatz
commented
2 years ago Note: @askuric will be delayed in starting their review until 25 Sept.
danielskatz
commented
2 years ago @untzag and @askuric - Thanks for agreeing to review this submission. This is the review thread for the paper. All of our communications will happen here from now on.
As you can see above, you each should use the command @editorialbot generate my checklist to create your review checklist. @editorialbot commands need to be the first thing in a new comment.
As you go over the submission, please check any items that you feel have been satisfied. There are also links to the JOSS reviewer guidelines.
The JOSS review is different from most other journals. Our goal is to work with the authors to help them meet our criteria instead of merely passing judgment on the submission. As such, reviewers are encouraged to submit issues and pull requests on the software repository. When doing so, please mention openjournals/joss-reviews#4762 so that a link is created to this thread (and I can keep an eye on what is happening). Please also feel free to comment and ask questions on this thread. In my experience, it is better to post comments/questions/suggestions as you come across them instead of waiting until you've reviewed the entire package.
We aim for reviews to be completed within about 2-4 weeks. Please let me know if either of you require some more time. We can also use editorialbot (our bot) to set automatic reminders if you know you'll be away for a known period of time.
Please feel free to ping me (@danielskatz) if you have any questions/concerns.
danielskatz
commented
2 years ago 👋 @Ajstros (Abraham Stroschein) - please work on the possibly missing DOI and incorrectly prefixed DOI that editorialbot suggests, but note that the missing one may be incorrect. Please feel free to make changes to your .bib file, then use the command @editorialbot check references to check again, and the command @editorialbot generate pdf when the references are right to make a new PDF. editorialbot commands need to be the first entry in a new comment.
Ajstros
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2 years ago @editorialbot check references
editorialbot
commented
2 years ago Reference check summary (note 'MISSING' DOIs are suggestions that need verification):
OK DOIs
- 10.1063/1.5001312 is OK
- 10.1016/j.bpj.2021.11.1391 is OK
- 10.5281/zenodo.777229 is OK
- 10.5281/zenodo.3732545 is OK
- 10.1080/08940886.2019.1608121 is OK
MISSING DOIs
- 10.1145/2851581.2890266 may be a valid DOI for title: FrontPanel®
INVALID DOIs
- None@editorialbot generate pdf
editorialbot
commented
2 years ago :point_right::page_facing_up: Download article proof :page_facing_up: View article proof on GitHub :page_facing_up: :point_left:
Ajstros
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2 years ago @danielskatz Thank you for the note. The invalid DOI has been fixed, and the suggested missing DOI is incorrect.
danielskatz
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2 years ago 👋 @untzag and @askuric - please go ahead and use the command @editorialbot generate my checklist to create your review checklist. @editorialbot commands need to be the first thing in a new comment. Then you can get started on your reviews, and track which criteria you feel are satisfied by the submission and which need discussion with or action from the author
askuric
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2 years ago 
untzag
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2 years ago untzag
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2 years ago @Ajstros you might want to look into formatting details for your paper, some of the lines are escaping the page.
Ajstros
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2 years ago @editorialbot generate pdf
editorialbot
commented
2 years ago :point_right::page_facing_up: Download article proof :page_facing_up: View article proof on GitHub :page_facing_up: :point_left:
Ajstros
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2 years ago Thanks @untzag, those lines have been fixed now.
askuric
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2 years ago Hi everyone, My review of Pyripherals is here:
Pyripherals is a python pip package facilitating the communication to different FPGA based peripheral devices. It provides an user-friendly abstraction layer to different communication protocols and implements interfaces to many different standard FPGA based data acquisition devices. This all makes Pyripherals an useful tool for setting up an experiments requiring real-time data exchange.
Text:
py -m pytest -m usable, I am not sure if it's just me by py does not work only with pytest installed. I'd suggest to use python -m pytest -m usable.danielskatz
commented
2 years ago @Ajstros - can you respond to the comments from @askuric above?
danielskatz
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2 years ago Thanks @untzag, those lines have been fixed now.
@untzag - can you now make further progress on your review? Or is anything blocking you?
Ajstros
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2 years ago Yes, I will work on addressing those comments this week. Thanks for the feedback!
untzag
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2 years ago Just waiting for some more time, sorry to be slow! Working on review again now.
untzag
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2 years ago Similar DAQ systems (Leibrandt & Heidecker, 2015; Yu et al., 2018) create MHz bandwidth servos for physics experiments but these works do not expose the host software.
To me, it's unclear what you mean by "expose" here. I think you mean that their host software is not open source or freely available? I think for me it's down to the word "expose", consider choosing a different word.
untzag
commented
2 years ago Quoting from @askuric
Maybe it would be a good idea to add a paragraph at the begging of the Summary section explaining in broad terms the functioanllity of the code and the general stracture. We have a PC, a FPGA and the communication protoclo which has registers and endpoints.
As somebody who is a little bit further away from the FPGA world, I strongly advise you to add some more description here. Your statement of need is motivating---I would LOVE to have microsecond latency real-time feedback in some of the instruments I'm responsible for. Personally I cannot discern the big picture of how pyripherals fits into this system.
Here's my best attempt to describe what we have here. I'm wrong I'm sure, but perhaps my lack of understanding will be illustrative :smile:
Presumably the host python <-> FPGA bus is not particularly real-time, so where does my real-time feedback live?
Honestly as I write this out it gets more confusing. Again I'm not in the FPGA world so I'm going to need it spelled out slowly. I think new users of pyripherals might be in a similar place.
untzag
commented
2 years ago Quoting again from @askuric
You could also look into setting up the testing procedure using github CI (the github actions). That way every github commit would be automatically tested.
In my opinion this should be blocking for publication. This is a good opportunity to get real CI set up and running.
I understand that many of these code paths aren't possible to run without hardware, but you do have no_fpga tests. Even just showing that the package can be installed and imported with CI is useful for dealing with potential chaos from new contributors.
As long as you're working on CI, consider adding a workflow for publishing to PyPI---that's a great feature for a package that's going to get worked on by multiple people.
untzag
commented
2 years ago Pyripherals seems like a great project and it's clearly a powerful tool which has already been used to drive a variety of experiments. I'm thinking I need to buy an OpalKelly FPGA! I recommend publication and congrats on the great work.
I think pyripherals needs one more round of documentation work with an eye towards high-level explanation for outsiders wanting to start from scratch. You've built a system with a lot of moving parts, and it's opaque to me as a reader how those fit together into an experimental control system. I think you can expect a basic understanding of busses, registers, and the concept of a Python API---but readers like me need help with the layers between.
danielskatz
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2 years ago @untzag - I'll just point out here that JOSS's criterion on testing does not require automated testing, so while I think that using CI would be great, it shouldn't be a blocker for acceptance.
Again, your suggestions (CI & PyPI) are great and would really benefit the software and the community, but they are not strictly required by JOSS
Quoting again from @askuric
You could also look into setting up the testing procedure using github CI (the github actions). That way every github commit would be automatically tested.
In my opinion this should be blocking for publication. This is a good opportunity to get real CI set up and running.
I understand that many of these code paths aren't possible to run without hardware, but you do have
no_fpgatests. Even just showing that the package can be installed and imported with CI is useful for dealing with potential chaos from new contributors.As long as you're working on CI, consider adding a workflow for publishing to PyPI---that's a great feature for a package that's going to get worked on by multiple people.
lucask07
commented
2 years ago @untzag, @danielskatz, @askuric Thank you so much for the great feedback and we really appreciate your time! We (@Ajstros) are working through these and will get back to you soon. Sorry for the slow response. One of us is an undergraduate student taking too many courses and the other is trying to teach 3 courses.
I completely agree that there are many moving parts. We will take a careful look at the paper and the documentation to try to help new users get started.
Pyripherals is a general Python solution to organize and interface to chips with registers but in our lab, we exclusively use it to interface with the FPGA design here: https://github.com/lucask07/covg_fpga
lucask07
commented
2 years ago Quoting from @askuric
Maybe it would be a good idea to add a paragraph at the begging of the Summary section explaining in broad terms the functioanllity of the code and the general stracture. We have a PC, a FPGA and the communication protoclo which has registers and endpoints.
As somebody who is a little bit further away from the FPGA world, I strongly advise you to add some more description here. Your statement of need is motivating---I would LOVE to have microsecond latency real-time feedback in some of the instruments I'm responsible for. Personally I cannot discern the big picture of how pyripherals fits into this system.
Here's my best attempt to describe what we have here. I'm wrong I'm sure, but perhaps my lack of understanding will be illustrative 😄
* users create register spreadsheets corresponding to IC internalsCorrect
* all ICs are connected to FPGAYes. This may require a custom circuit board that the ICs are mounted to (e.g. https://github.com/lucask07/open_covg_daq_pcb). An ADC evaluation board or for example a ToF sensor eval board.
* pyripherals somehow tells the FPGA about which ICs are connected to which buses, and which registers those ICs haveThere is a file (ep_defines.v) that is shared between Verilog and pyripherals. This file specifies the addresses of each communication controller (e.g. SPI controller) that is instantiated in the FPGA. The FPGA does not know which registers the IC has. Pyripherals knows the registers and sends the message through the FPGA to the IC.
* does this involve verilog code generation?Yes, this requires verilog but not verilog "code generation".
* pyripherals offers a python interface to the ICs where the FPGA somehow acts as a host bus adapterYes, and the FPGA is a host bus adapter for multiple interfaces (SPI, I2C, LVDS, etc.).
Presumably the host python <-> FPGA bus is not particularly real-time, so where does my real-time feedback live?
In the FPGA via digital signal processing. ADC data can be scaled and filtered and then drive DAC(s). You are correct that this does not go through the python <-> FPGA bus. Real-time feedback is a motivator for an FPGA and peripherals (ADCs and DACs) but not a motivator directly for pyripherals. For real-time feedback experiments pyripherals first initializes ADCs (sets pre-amp gain or filter bandwidth) and DACs before control is handed off to the FPGA.
Honestly as I write this out it gets more confusing. Again I'm not in the FPGA world so I'm going to need it spelled out slowly. I think new users of pyripherals might be in a similar place.
Totally agree, we have some documentation work to do!
danielskatz
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2 years ago 👋 @lucask07 - no hurry, but can you let us know when you think there will be some changes for the reviewers to look at?
Ajstros
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2 years ago @untzag @askuric Sorry for the delay, but the testing issue with no_fpga tests has been fixed. You should now be able to run those tests with or without a config.yaml file regardless of the ep_defines_path value. These tests have also been added to a GitHub workflow run on any commit or pull request to the main branch.
lucask07
commented
2 years ago @danielskatz Thanks for checking in. We have updated the code so that the pytest issue does not occur for the testers without an FPGA (both reviewers). In the process, @Ajstros also set up continuous integration (CI) for tests on pull requests and commits to the main branch.
We still need to incorporate changes to the paper and rthe documentation to address the concerns and questions of both reviewers. I suspect this will take another week. The reviewers can plan for an update to revisit by Fri Oct 28.
danielskatz
commented
2 years ago @editorialbot remind @danielskatz in 8 days
editorialbot
commented
2 years ago @danielskatz doesn't seem to be a reviewer or author for this submission.
danielskatz
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2 years ago @editorialbot remind @danielskatz in 4 days
editorialbot
commented
2 years ago Reminder set for @danielskatz in 4 days
lucask07
commented
2 years ago Hi everyone, My review of Pyripherals is here:
Pyripherals
Pyripherals is a python pip package facilitating the communication to different FPGA based peripheral devices. It provides an user-friendly abstraction layer to different communication protocols and implements interfaces to many different standard FPGA based data acquisition devices. This all makes Pyripherals an useful tool for setting up an experiments requiring real-time data exchange.
Paper comments
Text:
* line 12: "yet the Python developments are generally useful to interface to electronic chips containing registers." * Maybe a bit too general, as all the electronics chips and microcontrollers contain registers at some level. Maybe you could you be a bit more specific and say that it is for the "communication".
This has been rewritten to "yet the Python developments are generally useful to organize communication with peripheral chips."
* line 37: " The Opal Kelly XEM7310 FPGA that we use for communication controllers to demonstrate pyripherals is common in research environments which allows other labs to accelerate their development of FPGA to electronic chip interfaces using pyripherals." * Some commas are probably necessary here :D
This has been rewritten to "The Opal Kelly XEM7310 FPGA that we use for communication controllers to demonstrate pyripherals is common in research environments such that our pyripherals software may accelerate developments of FPGA to electronic chip interfaces in other labs."
* table page 2: * It would be maybe good to have a caption and to explain each one of the table entries to the reader, as not everyone will be able to understand those. And maybe refer how the name 'ABC012' corresponds to the table entries, if it does. If it doesn't, maybe it would be a good idea to use a more descriptive name that 'ABC012', like 'MyPeripheral' or something like that.
Agreed, this has been changed to 'MYADC'.
* line 69: "The line below shows an example that defines an endpoint named “WRITE_IN” that belongs to peripheral “ABC012” with an address of 0x04 and a bit_width of 32 that adds 7 to the address every time it is advanced." * I would suggest to add a sentence or two before this line (or after the line 65) to explain what the endpoint actually is and how it is defined. It would probably be easier to understand each of the parameters than learning it directly from the example.
We have added a table caption: "Table 1: Each row shows a bit-field with a name and an address. This information is typically extracted from the datasheet of the peripheral chip. Addressable registers in a peripheral have multiple bits (often 16 or 32) that allow multiple data fields to be held in each register. To account for this, the location within a register is indicated by the high and low bit index columns. The default value of the register is stored to support verification of communication by checks of read-only registers."
* I'd also suggest to change the name of the endpoint to something more descriptive, "WRITE_IN" an input I imagine, but an input of the FPGA or the PC? * Also, maybe it would be a good idea to mention that the 8'h means 8 bit hex number for the sake of clarity, even though it is described in the documentation.
We added the sentence: "Endpoint directions are from the perspective of the FPGA so WRITE_IN is data from the host computer into the FPGA that is destined for the ADC chip."
We added:
"(the 8'h prefix below is Verilog syntax that indicates an 8-bit hexademical number)"
* line 86: "Using the Endpoint class in pyripherals with a definitions file extends the capabilities of the Opal Kelly FrontPanel API by automatically linking the Python and Verilog endpoint data. * Few commas missing, maybe also repharse it to be more clear.
We have rewritten this to:
"The Endpoint class in pyripherals extends the capabilities of the Opal Kelly FrontPanel API by automatically linking the Python and Verilog endpoint data with a shared definitions file."
* Something to consider * Maybe it would be a good idea to add a paragraph at the begging of the Summary section explaining in broad terms the functioanllity of the code and the general stracture. We have a PC, a FPGA and the communication protoclo which has registers and endpoints. * Also there you coul add a schematic of the peripheral communication showing a PC, FPGA, the communication and maybe endpoints or registers, I'm not sure how it should look exactly. But a visual could help in understanding better all the components.
Great idea! We added a figure at the start of the paper Summary section with a detailed caption. We hope this figure addresses your concerns of a missing high-level summary.
Documentation commnets
* tests: * the line `py -m pytest -m usable`, I am not sure if it's just me by `py` does not work only with `pytest` installed. I'd suggest to use `python -m pytest -m usable`. * I've also have one of the tests failing: [[JOSS REVIEW] tests no_fpga failing Ajstros/pyripherals#22](https://github.com/Ajstros/pyripherals/issues/22) * You could also look into setting up the testing procedure using github CI (the github actions). That way every github commit would be automatically tested. * Community guidelines: * You have a very nice guide for contributing the new peripheral. * However it might be a good idea to make it more general, if people are motivated to contribute by adding a functionality to the existing code, correcting bugs, improve the code efficiency or any other form of contribution.
We believe that the contributions guide is sufficient.
Code comments
* The code is well structured and written, and the unit tests are provided. * I was not able to test the functionality of the code as I do not have the hardware necessary.
The "no_fpga" tests are working now. Please see: https://github.com/Ajstros/pyripherals/issues/22 To try these tests again please pull the updated repository.
* The installation procedure is well documented and I had no trouble installing the package and running simple examples.
Thank you for your thorough review!
lucask07
commented
2 years ago @editorialbot generate pdf
editorialbot
commented
2 years ago :point_right::page_facing_up: Download article proof :page_facing_up: View article proof on GitHub :page_facing_up: :point_left:
lucask07
commented
2 years ago Hi @danielskatz We have completed our code fixes and paper/documentation upgrades in response to the feedback from the reviewers. The brief summary is:
lucask07
commented
2 years ago Quoting again from @askuric
You could also look into setting up the testing procedure using github CI (the github actions). That way every github commit would be automatically tested.
In my opinion this should be blocking for publication. This is a good opportunity to get real CI set up and running.
I understand that many of these code paths aren't possible to run without hardware, but you do have
no_fpgatests. Even just showing that the package can be installed and imported with CI is useful for dealing with potential chaos from new contributors.As long as you're working on CI, consider adding a workflow for publishing to PyPI---that's a great feature for a package that's going to get worked on by multiple people.
Great idea, CI for tests upon on push to GitHub have been setup.
lucask07
commented
2 years ago Similar DAQ systems (Leibrandt & Heidecker, 2015; Yu et al., 2018) create MHz bandwidth servos for physics experiments but these works do not expose the host software.
To me, it's unclear what you mean by "expose" here. I think you mean that their host software is not open source or freely available? I think for me it's down to the word "expose", consider choosing a different word.
Good point. This has been rewritten to "but the host software is either not publicly available or not generalizable."
editorialbot
commented
2 years ago :wave: @danielskatz, please take a look at the state of the submission (this is an automated reminder).
danielskatz
commented
2 years ago 👋 @askuric - can you take a look at this again?
And thanks for your updates & responses @lucask07.
askuric
commented
1 year ago Hi everyone,
Sorry for keeping you waiting. The paper looks good to me and the changes address all of my comments, so from my side it is ready for publishing. Great work @lucask07 and @Ajstros.
lucask07
commented
1 year ago Thank you @askuric for your time!
If you feel ok with it can you check off the last box in your checklist of "Summary: Has a clear description of the high-level functionality and purpose of the software for a diverse, non-specialist audience been provided?"
askuric
commented
1 year ago Ah yes, I've forgotten about that. Done.
Submitting author: !--author-handle-->@Ajstros<!--end-author-handle-- (Abraham Stroschein) Repository: https://github.com/Ajstros/pyripherals Branch with paper.md (empty if default branch): Version: v0.0.3 Editor: !--editor-->@danielskatz<!--end-editor-- Reviewers: @untzag, @askuric Archive: 10.5281/zenodo.7308636
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