openpowerwtf
commented
3 years ago This should help.
6.7 Effective to Real Address Translation Arrays
When operating in MMU mode, the on-demand replacement of entries in the ERATs is managed by hardware in a pseudo least-recently-used (LRU) fashion. Upon an ERAT miss that leads to a UTLB hit, the hardware automatically casts-out the oldest entry in the ERAT and replaces it with the new translation.
The eratwe instruction with the WS = 3 setting is used in the A2 implementation to set a hardware LRU watermark register for each of the ERAT facilities. This can be leveraged directly in certain kernel applications to “reserve” some number of translation entries for the kernel to be “immune” to replacement, especially with a backing hardware MMU TLB replacement scheme. This feature allows for “pinning” of some number of ERAT entries above the watermark value that are managed by software. The entries at or below the watermark are candidates for hardware replacement via normal LRU selection. See Section 6.7.5 ERAT LRU Replacement Watermark for more details on this feature.
I spent one week reading the source code in I-ERAT to understand how LRU algorithm works. Until now, I still do not find the right way to read the code. I am totally lost in the combination logics. I guess the key algorithm or implementation of LRU does not have too many codes but the watermark and other SPR operations compliate the design a lot.
Can someone give me any help about how to quickly understand the LRU algorithm in A2I? I know the classic LRU algorithm which is widely taught in the computer courses... Here, it seems to me to be a totally different LRU compared to what I learned before:))