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How to match the coming effective/virtual address with the given TLB entry when considering the X _bit? #20

Closed luffygood closed 3 years ago

luffygood commented 3 years ago

In the mmq_tlb_matchline.vhdl, there have 2 kinds of signals: function_34_51 <= not(entry_xbit) or not(pgsize_eq_1G) or or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); -- 256M function_36_51 <= not(entry_xbit) or not(pgsize_eq_256M) or or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); -- 16M function_40_51 <= not(entry_xbit) or not(pgsize_eq_16M) or or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); -- 1M function_44_51 <= not(entry_xbit) or not(pgsize_eq_1M) or or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); -- 64K function_48_51 <= not(entry_xbit) or not(pgsize_eq_64K) or or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));

comp_or_48_51 <= and_reduce(match_line(48 to 51)) or pgsize_gte_64K; comp_or_44_47 <= and_reduce(match_line(44 to 47)) or pgsize_gte_1M; comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G;

When the xbit exists, what does the signals function_n_51 and comp_or_n1_n2 mean? And what do they actually do when matching the effective/virtual address with the TLB entry?

luffygood commented 3 years ago

It looks like I really need some help to understand the relation between the signals below:

  pgsize_gte_1G   <= entry_cmpmask(0);
  pgsize_gte_256M <= entry_cmpmask(1);
  pgsize_gte_16M  <= entry_cmpmask(2);
  pgsize_gte_1M   <= entry_cmpmask(3);
  pgsize_gte_64K  <= entry_cmpmask(4);
  pgsize_eq_1G   <= entry_xbitmask(0);
  pgsize_eq_256M <= entry_xbitmask(1);
  pgsize_eq_16M  <= entry_xbitmask(2);
  pgsize_eq_1M   <= entry_xbitmask(3);
  pgsize_eq_64K  <= entry_xbitmask(4);

This is my understand. The signals pgsize_eq_size describe that the pagesize of the TLB entry is equal to the size. The signals pgsize_gte_size describe that the pagesize of the TLB entry is greater than or equal to the size. For example, if the pagesize of the TLB entry is 256M at beginning, when we make a hole in this TLB entry, then its pagesize is not equal to 256M but greater than 16M. So the signal pgsize_gte_16M means that there has a hole in the TLB entry whose pagesize is 256M at beginning. Is my understanding correct? Thanks for your help.

luffygood commented 3 years ago

It looks like I really need some help to understand the relation between the signals below:

  pgsize_gte_1G   <= entry_cmpmask(0);
  pgsize_gte_256M <= entry_cmpmask(1);
  pgsize_gte_16M  <= entry_cmpmask(2);
  pgsize_gte_1M   <= entry_cmpmask(3);
  pgsize_gte_64K  <= entry_cmpmask(4);
  pgsize_eq_1G   <= entry_xbitmask(0);
  pgsize_eq_256M <= entry_xbitmask(1);
  pgsize_eq_16M  <= entry_xbitmask(2);
  pgsize_eq_1M   <= entry_xbitmask(3);
  pgsize_eq_64K  <= entry_xbitmask(4);

This is my understand. The signals pgsize_eq_size describe that the pagesize of the TLB entry is equal to the size. The signals pgsize_gte_size describe that the pagesize of the TLB entry is greater than or equal to the size. For example, if the pagesize of the TLB entry is 256M at beginning, when we make a hole in this TLB entry, then its pagesize is not equal to 256M but greater than 16M. So the signal pgsize_gte_16M means that there has a hole in the TLB entry whose pagesize is 256M at beginning. Is my understanding correct? Thanks for your help.