Closed Grubby-CPU closed 4 years ago
I would assume that logic that is very low-level like this was copied/updated from a previous version, and/or written specifically for timing/PD reasons. It's essentially a 'netlist' version, to be synthesized 1:1; something like a hard macro, but not quite . This appears to be implementing some piece of the adder without XOR's, so this was likely critical logic; maybe it had slightly better performance vs. a synthesized version, and got repeatable results across synthesis runs by controlling cells/fanouts/etc.
If you want to understand it, you'll have to figure out the combinational functions and rewrite in a more human-readable form.
Hi openpowerwtf, Thanks! The remaining question is how to figure out the combinational functions:)) Any suggestions or recommended tools?
No, it's ugly when the logic is written like that. You can try to reconstruct it bottom-up, but it may not be obvious what it's doing even if you turn it into higher-level equations. I would start top top-down and see where the macros fit in. If you can guess something is a CLA, CSA, etc., or a piece of one, you can check some of the logic inside to see if it makes sense. Then if you really want to verify it, do a simple testbench with just the macro and see if the function matches what you thought.
Hi Guys,
In A2I, there are so many combination logics. For example, in the xuq_add_loc.vhdl file, there are many "and", "or", "not" gates as shown below.
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` I know this file is related to the ALU add operation but I have no idea about how it works. Any idea about how to read these codes?
Many thanks