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L1 cache interface #26

Closed darwin964 closed 3 years ago

darwin964 commented 3 years ago

Hi，in order to implement L2 cache, we want to make an block level testbench contain L1 and L2 cache，how could I get the L1 interface? or get L1 rtl block?

openpowerwtf commented 3 years ago

The L1 I/D caches are part of the core rtl.

This is the spec for the core interface: A2L2 Spec

darwin964 commented 3 years ago

@openpowerwtf Is A2 designed by full custom?

openpowerwtf commented 3 years ago

No, I don't think any of the random logic was custom.

darwin964 commented 3 years ago

thanks

openpowerwtf commented 3 years ago

Don't forget - BlueGene ran at a slow frequency to balance system power/perf. Would have to synthesize to real technology today to see what the critical paths are; very likely some are around arrays.