Any hints about the ignore_flush_is0 signal

[zhaoxiahust]

Hi guys,

I cannot clearly understand the below code and the related comments. Can anyone give me more hints about this? What does " before or after the "real" fxu selection" mean?

`-- During fdiv/fsqrt the axu may select this thread before or after the "real" fxu selection.

-- If the axu selects this thread earlier than the fxu, s1 is simply updated early.

-- If the axu selects this thread later than the fxu, ucode instructions would get wiped out by the flush

-- This signal protects the instruction from being flushed

ignore_flush_is0 <= (fdiv_is0 or fsqrt_is0) and isfu_dec_is0; -- these opcodes will not change the FpScr or any Fpr. Only scratch reg s0 will be changed `

Many thanks

[openpowerwtf]

I'm not sure - you will have to trace through those signals. But those are 'special' ops in general - div/sqrt are always done as extended-execution ops, and usually raise a signal when complete (they iterate and typically are reusing pipe resources, so have to stall behind them). Since the comment also mentions the scratch reg, I would guess they are also microcoded.

Let me know if you find out anything more...