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Question regarding how to drive signal ac_an_req_ld_xfr_len and ac_an_req_ttype (hwsync) of a2l2_axi.vhdl in simulation. #35

Closed xinyu8888 closed 3 years ago

xinyu8888 commented 3 years ago

@openpowerwtf When we set req_ld_xfr_len to b’111 (32 bytes) for load ttype in simulation, we didn’t get correct reld_data. We only saw the first 16 bytes on reld_data and the last 16 bytes were missing, but it looked good on axi_rdata. It worked fine with req_ld_xfr_len being set to other values apart from b’111. Is there any specific requirement for driving this signal in simulation?

Under what kind of circumstances should we use hwsync (req_ttype=b’101011) in smulation? Would it affect the performance of L2 cache if we didn’t use it at all? Thx!

openpowerwtf commented 3 years ago

If Len=32 was ever used, it was only for the BGQ version that had a different FPU (mentioned in the A2L2 spec); shouldn't see it generated by this core.

Sync's are only used for multithread/processors, for storage ordering. The ISA describes the op and other cases where you might need it.