I am running the simulation of 4 threads together to test the issue unit. Here is the source code of the program which is super easy.
Below is the simulation wave and I find some problems with the i_afi_is2_take signal.
In particular, in the time area which is highlighted with the vertical red line, the value of i_afi_is2_take[0] keeps high. This is because "addi 17, 7, 10" instruction of thread0 is stalled in the iuq_fxu_issue unit. Meanwhile, the "fadd 7, 4, 5" instruction already enters the iuq_axu_fu_dec unit and pull the signal i_afd_is1_instr_v and signal i_axu_is1_early_v high. The iuq_axu_fu_iss unit then sets iu_is2_take_t[0], i.e., i_afi_is2_take[0], high.
I noticed that the value of i_afi_is2_take[0] keeping high will not affect the correctness since the signal i_afd_is2_t0_instr_v is low. However, I think the incorrect value of i_afi_is2_take will affect the scheduling scheme since the scheduling counter will increase. Any comments?
Dear all,
I am running the simulation of 4 threads together to test the issue unit. Here is the source code of the program which is super easy.
Below is the simulation wave and I find some problems with the i_afi_is2_take signal.
In particular, in the time area which is highlighted with the vertical red line, the value of i_afi_is2_take[0] keeps high. This is because "addi 17, 7, 10" instruction of thread0 is stalled in the iuq_fxu_issue unit. Meanwhile, the "fadd 7, 4, 5" instruction already enters the iuq_axu_fu_dec unit and pull the signal i_afd_is1_instr_v and signal i_axu_is1_early_v high. The iuq_axu_fu_iss unit then sets iu_is2_take_t[0], i.e., i_afi_is2_take[0], high.
I noticed that the value of i_afi_is2_take[0] keeping high will not affect the correctness since the signal i_afd_is2_t0_instr_v is low. However, I think the incorrect value of i_afi_is2_take will affect the scheduling scheme since the scheduling counter will increase. Any comments?
Many thanks