meeg
commented
3 hours ago The error you're getting (where Vivado picks a random top module for the project, and then complains that the design is empty) is something that I've seen before when there is some error when running the proj.tcl and the project didn't get fully configured.
Also, just to make sure . . . from your description of what you did, it's not clear to me whether you're following the right procedure. Are you following the instructions under "Building the firmware yourself" in https://github.com/openquantumhardware/qick/blob/main/firmware/README.md?
Could you delete your project, rerun proj.tcl, and look for errors in the tcl console? It's normal to have a lot of (harmless) warnings there, but there should not be any errors.
Hi,
I am currently trying to follow the instructions for generating the firmware for the RFSoC 4x2 board and I am having issues loading generating a bitstream.
Here's what I do: I am using Vivado 2022.1 and the board files, IPs, HDL, XDC etc from https://github.com/openquantumhardware/qick/tree/main/firmware/projects/qick_tprocv1_4x2_standard I set up a new project and run bd_2022-1.tcl in Vivado. My board design looks like in the attached picture. How can I verify, if the design has been created correctly?
When I start the synthesis the result is a Synthesis with 0 LUTs 0 FF etc. Accordingly, the implementation returns the error message that the design is empty:
[Place 30-494] The design is empty Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports. [Common 17-69] Command failed: Placer could not place all instances
Vivado automatically selects "tb_switch.sv" as a top module. Is that correct? Maybe these are stupid questions, but I am stuck at this point and would appreciate any kind of support.