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openrisc / mor1kx

mor1kx - an OpenRISC 1000 processor IP core
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Fix issues related to successive mtspr/mtspr instructions #124

Closed stffrdhrn closed 3 years ago

stffrdhrn commented 3 years ago

Issue #122

Writing to the tlb rams was dependent on the spr_bus_ack as a means to only write during the first cycle after a spr_bus_stb_i. This works fine for a single write, but if we have a write to itlb_match_spr followed by itlb_trans_spr the spr_bus_ack never goes low so the write to itlb_trans_spr is skipped.

Fix this by using the itlb_match_spr_cs_r and itlb_trans_spr_cs_r signals to control the "first cycle after spr_bus_stb_i" condition. This way writes can happen independently.

Note, there may still be issues with a write to itlb_match followed by another write to itlb_match. Fixing that requires changing the "first cycle after spr_bus_stb_i" policy, which is similar to dmmu.

stffrdhrn commented 3 years ago

This should fix all of #122 now as the test case passes for me know. This also fixes a trivial issue found related to cache hits not being forwarded to the performance counters.

stffrdhrn commented 3 years ago

If anyone has time please help review @olofk @bandvig @wallento @juliusbaxter @skristiansson, it does pass tests.