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openrisc / mor1kx

mor1kx - an OpenRISC 1000 processor IP core
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spr_bus_ack_o reset issue #127

Closed Harshitha172000 closed 3 years ago

Harshitha172000 commented 3 years ago

This issue is applicable to the mor1kx_icache module. After resetting, the state moves to IDLE but spr_bus_ack_o can be high if spr strobe/write signals stays high during reset. This is possible as spr stb/we signals are not reset in the ctrl module.

Assertion Failed:

          always @(posedge clk)
               if ($past(rst) && f_past_valid)
                  assert (!spr_bus_ack_ic_i);

Trace showing issue:

image

stffrdhrn commented 3 years ago

I posted a fix for this does it also fix formal?

Harshitha172000 commented 3 years ago

No, now I see this trace. With the reset, the state switches from INVALIDATE to IDLE and keeps spr_bus_ack_o high.

image

stffrdhrn commented 3 years ago

OK, it doesn't cater for the case when spr_bus_ack_o is high to start with.

stffrdhrn commented 3 years ago

I pushed another update, how does it look now?

Harshitha172000 commented 3 years ago

It passes the test, the issue is resolved.