openrisc / mor1kx

mor1kx - an OpenRISC 1000 processor IP core
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Setting dcache cache width to 2 or 3 causes failures #153

Open stffrdhrn opened 2 years ago

stffrdhrn commented 2 years ago

This can be tested by setting the cache with in mor1k_dcache.sby and running make -C bench/formal mor1kx_dcache.

It seems the generator logic does not work with smaller cache widths.