openrisc / mor1kx

mor1kx - an OpenRISC 1000 processor IP core
Other
485 stars 146 forks source link

[BUG] misaligned exception on SWA #97

Open JaewonHur opened 4 years ago

JaewonHur commented 4 years ago

Following the spec, SWA instruction should store a value to the specified address only when the atomic-reserve is set. If atomic-reserve is not set, SWA should not do any store. SWA with misaligned address should not assert any exception if atomic-reserve is not set. It seems mor1kx asserts exception in the above case.

following insn streams will reproduce

18000000 //l.movhi r0,0x0000   
a8200001 // l.ori   r1,r0,0x0001  
c0000811 // l.mtspr r0,r1,0x0011    
c1400000 // l.mtspr r0,r0,0x5000 
18000000 // l.movhi r0,0x0000
a8200001 // l.ori r1,r0,0x0001
18a0dead // l.movhi r5,0xdead
a8a5beef // l.ori r5,r5,0xbeef
cc802801 // l.swa 0x2001(r0),r5

following should solve this issue in mor1kx_lsu_cappuccino.v change assign except_align

assign except_align = ctrl_op_lsu & align_err & !(ctrl_op_lsu_store_i & ctrl_op_lsu_atomic_i & !atomic_reserve);
stffrdhrn commented 4 years ago

Thanks, this sounds reasonable.